57 lines
1.1 KiB
Systemverilog
57 lines
1.1 KiB
Systemverilog
module simple_coverage();
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logic [7:0] data;
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logic [7:0] addr;
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logic par;
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logic rw;
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logic en;
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// covergroup
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covergroup memory @ (posedge en);
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option.per_instance = 1;
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address : coverpoint addr {
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bins low = {0,50};
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bins med = {51,150};
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bins high = {151,255};
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}
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parity : coverpoint par {
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bins even = {0};
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bins odd = {1};
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}
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read_write : coverpoint rw {
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bins read = {0};
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bins write = {1};
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}
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endgroup
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// instance of covergroup
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memory mem = new();
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// drive stimulus
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task drive (input [7:0] a, input [7:0] d, input r);
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#5;
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en <= 1;
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addr <= a;
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rw <= r;
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data <= d;
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par <= ^d;
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#5;
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en <= 0;
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rw <= 0;
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data <= 0;
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par <= 0;
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addr <= 0;
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rw <= 0;
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endtask
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// stimulus generation
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initial begin
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en = 0;
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repeat (10) begin
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drive ($random, $random, $random);
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end
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#10 $finish;
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end
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endmodule : simple_coverage
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