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2026-06-12 07:53:32 +02:00
commit 59e71f3297
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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_agent.sv
DESCRIPTION
****************************************************************************/
`ifndef RESET_AGENT_SV
`define RESET_AGENT_SV
// reset sequencer
typedef uvm_sequencer#(reset_transaction) reset_sequencer;
/**
* Class: reset_agent
*/
class reset_agent extends uvm_agent;
// configuration object
reset_config cfg;
// components
reset_sequencer seqr;
reset_driver drv;
reset_monitor mon;
// UVM factory registration
`uvm_component_utils_begin(reset_agent)
`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)
`uvm_component_utils_end
// new - constructor
function new (string name = "reset_agent", uvm_component parent = null);
super.new(name, parent);
endfunction : new
// UVM build_phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// get configuration object from db
if(!uvm_config_db#(reset_config)::get(this, "", "reset_config", cfg)) begin
`uvm_info("NOCONFIG", "Using default reset_config", UVM_LOW)
cfg = reset_config::type_id::create("cfg");
uvm_config_db#(reset_config)::set(this, "*", "reset_config", cfg);
end
// create driver and sequencer if agent is active
if(cfg.is_active == UVM_ACTIVE) begin
seqr = reset_sequencer::type_id::create("seqr", this);
drv = reset_driver::type_id::create("drv", this);
end
// always create monitor
mon = reset_monitor::type_id::create("mon", this);
endfunction : build_phase
// UVM connect_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
// connect driver and sequencer if agent is active
if(cfg.is_active == UVM_ACTIVE) begin
drv.seq_item_port.connect(seqr.seq_item_export);
end
endfunction : connect_phase
endclass : reset_agent
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_config.sv
DESCRIPTION configuration class for reset agent
****************************************************************************/
`ifndef RESET_CONFIG_SV
`define RESET_CONFIG_SV
/**
* Class: reset_config
*/
class reset_config extends uvm_object;
// reset value at the start of simulation
bit value_at_0 = 0;
// 1 = reset is active high; 0 = active low
bit active_high = 1;
// is agent active or passive
uvm_active_passive_enum is_active = UVM_ACTIVE;
// checks and coverage control
bit has_checks = 1;
bit has_coverage = 1;
// UVM factory registration
`uvm_object_utils_begin(reset_config)
`uvm_field_int(value_at_0, UVM_DEFAULT)
`uvm_field_int(active_high, UVM_DEFAULT)
`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)
`uvm_field_int(has_checks, UVM_DEFAULT)
`uvm_field_int(has_coverage, UVM_DEFAULT)
`uvm_object_utils_end
// new - constructor
function new(string name = "reset_config");
super.new(name);
endfunction : new
endclass : reset_config
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_driver.sv
DESCRIPTION drives reset
****************************************************************************/
`ifndef RESET_DRIVER_SV
`define RESET_DRIVER_SV
/**
* Class: reset_driver
*/
class reset_driver extends uvm_driver #(reset_transaction);
// reset virtual interface
virtual reset_if vif;
// configuration
reset_config cfg;
// UVM factory registration
`uvm_component_utils_begin(reset_driver)
`uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)
`uvm_component_utils_end
// new - constructor
function new (string name = "reset_driver", uvm_component parent = null);
super.new(name, parent);
endfunction : new
// UVM build_phase
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
// get configuration object from db
if(!uvm_config_db#(reset_config)::get(this, "*", "reset_config", cfg))
`uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
endfunction: build_phase
// UVM connect_phase
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
// get interface from db
if(!uvm_config_db#(virtual reset_if)::get(this, "", "reset_if", vif))
`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction : connect_phase
// additional class methods
extern virtual task run_phase(uvm_phase phase);
extern virtual function void start_of_simulation_phase(uvm_phase phase);
extern virtual task drive_tr (reset_transaction tr);
endclass : reset_driver
// UVM start_of_simulation_phase
function void reset_driver::start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
vif.reset <= cfg.value_at_0; // init reset
endfunction
// UVM run_phase
task reset_driver::run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
drive_tr(req);
seq_item_port.item_done();
end
endtask : run_phase
// Drives a transfer when an item is ready to be sent.
task reset_driver::drive_tr (reset_transaction tr);
`uvm_info( get_type_name(),
$sformatf("Driving reset: delay %0d clocks duration of %0d clocks",
tr.transmit_delay, tr.duration),
UVM_LOW)
// delay
if (tr.transmit_delay > 0) begin
repeat(tr.transmit_delay) @(posedge vif.clk);
end
// start reset
vif.reset <= cfg.active_high;
// duration
repeat(tr.duration) @(posedge vif.clk);
// drop reset
vif.reset <= ~cfg.active_high;
endtask : drive_tr
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_if.sv
DESCRIPTION reset interface
****************************************************************************/
`ifndef RESET_IF_SV
`define RESET_IF_SV
/**
* Interface: reset_if
*/
interface reset_if (input clk, output logic reset);
endinterface : reset_if
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_monitor.sv
DESCRIPTION monitors interface for reset; collects coverage
****************************************************************************/
`ifndef RESET_MONITOR_SV
`define RESET_MONITOR_SV
/**
* Class: reset_monitor
*/
class reset_monitor extends uvm_monitor;
// reset virtual interface
virtual reset_if vif;
// configuration
reset_config cfg;
// TLM - from monitor to other components
uvm_analysis_port #(reset_transaction) item_collected_port;
// keep track of number of transactions
int unsigned num_transactions = 0;
// current transaction
reset_transaction tr_collected;
// UVM factory registration
`uvm_component_utils_begin(reset_monitor)
`uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)
`uvm_component_utils_end
// coverage
covergroup cg_reset;
// reset duration
cp_duration : coverpoint tr_collected.duration {
bins one_clk = {1};
bins other = default;
}
endgroup : cg_reset;
// new - constructor
function new(string name = "reset_monitor", uvm_component parent = null);
super.new(name, parent);
item_collected_port = new("item_collected_port", this);
cg_reset = new();
endfunction : new
// UVM build_phase
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// get configuration object from db
if(!uvm_config_db#(reset_config)::get(this, "", "reset_config", cfg))
`uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
endfunction: build_phase
// UVM connect_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
// get interface from db
if(!uvm_config_db#(virtual reset_if)::get(this, "", "reset_if", vif))
`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction : connect_phase
// additional class methods
extern virtual task run_phase(uvm_phase phase);
extern virtual function void report_phase(uvm_phase phase);
endclass : reset_monitor
// UVM run_phase
task reset_monitor::run_phase(uvm_phase phase);
forever begin
tr_collected = reset_transaction::type_id::create("tr_collected");
// monitor reset
if(cfg.active_high) begin
@(posedge vif.reset);
end
else begin
@(negedge vif.reset);
end
`uvm_info(get_type_name(), "Reset observed", UVM_MEDIUM)
tr_collected.duration = 1;
fork
// get duration
forever begin
@(posedge vif.clk) tr_collected.duration++;
end
// monitor reset dropped
begin
if(cfg.active_high) begin
@(negedge vif.reset);
end
else begin
@(posedge vif.reset);
end
end
join_any
disable fork;
item_collected_port.write(tr_collected); // TLM
// collect coverage if enabled
if(cfg.has_coverage == 1) begin
cg_reset.sample();
end
num_transactions++;
end // forever begin
endtask : run_phase
// UVM report_phase
function void reset_monitor::report_phase(uvm_phase phase);
// final report
`uvm_info(get_type_name(), $sformatf("Report: reset monitor collected %0d transfers", num_transactions), UVM_LOW);
endfunction : report_phase
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_pkg.sv
DESCRIPTION package containing all parameters and includes
****************************************************************************/
`ifndef RESET_PKG_SV
`define RESET_PKG_SV
/**
* Package: reset_pkg
*/
package reset_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "reset_config.sv"
`include "reset_transaction.sv"
`include "reset_driver.sv"
`include "reset_monitor.sv"
`include "reset_agent.sv"
`include "sequences/reset_seq_lib.sv"
endpackage : reset_pkg
`include "reset_if.sv"
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_transaction.sv
DESCRIPTION reset sequence item
****************************************************************************/
`ifndef RESET_TRANSACTION_SV
`define RESET_TRANSACTION_SV
/**
* Class: reset_transaction
*/
class reset_transaction extends uvm_sequence_item;
// delay before asserting reset (#clk cycles)
rand int unsigned transmit_delay;
// duration of reset (#clk cycles)
rand int unsigned duration;
// constraints
constraint c_transmit_delay { transmit_delay <= 10; }
constraint c_duration { duration inside {[0:5]}; }
// UVM factory registration
`uvm_object_utils_begin(reset_transaction)
`uvm_field_int(transmit_delay, UVM_DEFAULT)
`uvm_field_int(duration, UVM_DEFAULT)
`uvm_object_utils_end
// new - constructor
function new (string name = "reset_transaction");
super.new(name);
endfunction : new
endclass : reset_transaction
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_base_seq.sv
DESCRIPTION base sequence
****************************************************************************/
`ifndef RESET_BASE_SEQ_SV
`define RESET_BASE_SEQ_SV
/**
* Class: reset_base_seq
*/
class reset_base_seq extends uvm_sequence #(reset_transaction, reset_transaction);
// UVM factory registration
`uvm_object_utils(reset_base_seq)
// new - constructor
function new(string name = "reset_base_seq");
super.new(name);
endfunction : new
endclass : reset_base_seq
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_seq.sv
DESCRIPTION sequence for assertion reset
****************************************************************************/
`ifndef RESET_SEQ_SV
`define RESET_SEQ_SV
/**
* Class: reset_seq
*/
class reset_seq extends reset_base_seq;
// delay before asserting reset (#clk cycles)
rand int unsigned transmit_del;
// duration of reset (#clk cycles)
rand int unsigned duration_time;
// UVM factory registration
`uvm_object_utils(reset_seq)
// constraints
constraint c_transmit_delay { transmit_del <= 10; }
constraint c_duration_time { duration_time inside {[1:5]}; }
// new - constructor
function new(string name = "reset_seq");
super.new(name);
endfunction : new
// sequence generation logic in body
virtual task body();
// send one transaction
`uvm_do_with(req, { req.duration == duration_time;
req.transmit_delay == transmit_del; } )
endtask : body
endclass : reset_seq
`endif

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/****************************************************************************
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
FILE reset_seq_lib.sv
DESCRIPTION sequence includes
****************************************************************************/
`ifndef RESET_SEQ_LIB_SV
`define RESET_SEQ_LIB_SV
`include "sequences/reset_base_seq.sv"
`include "sequences/reset_seq.sv"
`endif