init
This commit is contained in:
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_agent.sv
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DESCRIPTION
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****************************************************************************/
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`ifndef RESET_AGENT_SV
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`define RESET_AGENT_SV
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// reset sequencer
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typedef uvm_sequencer#(reset_transaction) reset_sequencer;
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/**
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* Class: reset_agent
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*/
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class reset_agent extends uvm_agent;
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// configuration object
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reset_config cfg;
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// components
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reset_sequencer seqr;
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reset_driver drv;
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reset_monitor mon;
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// UVM factory registration
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`uvm_component_utils_begin(reset_agent)
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`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)
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`uvm_component_utils_end
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// new - constructor
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function new (string name = "reset_agent", uvm_component parent = null);
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super.new(name, parent);
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endfunction : new
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// UVM build_phase
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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// get configuration object from db
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if(!uvm_config_db#(reset_config)::get(this, "", "reset_config", cfg)) begin
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`uvm_info("NOCONFIG", "Using default reset_config", UVM_LOW)
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cfg = reset_config::type_id::create("cfg");
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uvm_config_db#(reset_config)::set(this, "*", "reset_config", cfg);
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end
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// create driver and sequencer if agent is active
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if(cfg.is_active == UVM_ACTIVE) begin
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seqr = reset_sequencer::type_id::create("seqr", this);
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drv = reset_driver::type_id::create("drv", this);
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end
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// always create monitor
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mon = reset_monitor::type_id::create("mon", this);
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endfunction : build_phase
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// UVM connect_phase
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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// connect driver and sequencer if agent is active
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if(cfg.is_active == UVM_ACTIVE) begin
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drv.seq_item_port.connect(seqr.seq_item_export);
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end
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endfunction : connect_phase
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endclass : reset_agent
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`endif
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@@ -0,0 +1,46 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_config.sv
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DESCRIPTION configuration class for reset agent
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****************************************************************************/
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`ifndef RESET_CONFIG_SV
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`define RESET_CONFIG_SV
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/**
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* Class: reset_config
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*/
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class reset_config extends uvm_object;
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// reset value at the start of simulation
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bit value_at_0 = 0;
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// 1 = reset is active high; 0 = active low
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bit active_high = 1;
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// is agent active or passive
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uvm_active_passive_enum is_active = UVM_ACTIVE;
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// checks and coverage control
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bit has_checks = 1;
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bit has_coverage = 1;
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// UVM factory registration
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`uvm_object_utils_begin(reset_config)
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`uvm_field_int(value_at_0, UVM_DEFAULT)
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`uvm_field_int(active_high, UVM_DEFAULT)
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`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)
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`uvm_field_int(has_checks, UVM_DEFAULT)
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`uvm_field_int(has_coverage, UVM_DEFAULT)
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`uvm_object_utils_end
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// new - constructor
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function new(string name = "reset_config");
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super.new(name);
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endfunction : new
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endclass : reset_config
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`endif
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@@ -0,0 +1,93 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_driver.sv
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DESCRIPTION drives reset
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****************************************************************************/
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`ifndef RESET_DRIVER_SV
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`define RESET_DRIVER_SV
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/**
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* Class: reset_driver
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*/
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class reset_driver extends uvm_driver #(reset_transaction);
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// reset virtual interface
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virtual reset_if vif;
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// configuration
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reset_config cfg;
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// UVM factory registration
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`uvm_component_utils_begin(reset_driver)
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`uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)
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`uvm_component_utils_end
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// new - constructor
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function new (string name = "reset_driver", uvm_component parent = null);
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super.new(name, parent);
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endfunction : new
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// UVM build_phase
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virtual function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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// get configuration object from db
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if(!uvm_config_db#(reset_config)::get(this, "*", "reset_config", cfg))
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`uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
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endfunction: build_phase
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// UVM connect_phase
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virtual function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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// get interface from db
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if(!uvm_config_db#(virtual reset_if)::get(this, "", "reset_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
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endfunction : connect_phase
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// additional class methods
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extern virtual task run_phase(uvm_phase phase);
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extern virtual function void start_of_simulation_phase(uvm_phase phase);
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extern virtual task drive_tr (reset_transaction tr);
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endclass : reset_driver
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// UVM start_of_simulation_phase
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function void reset_driver::start_of_simulation_phase(uvm_phase phase);
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super.start_of_simulation_phase(phase);
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vif.reset <= cfg.value_at_0; // init reset
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endfunction
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// UVM run_phase
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task reset_driver::run_phase(uvm_phase phase);
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forever begin
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seq_item_port.get_next_item(req);
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drive_tr(req);
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seq_item_port.item_done();
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end
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endtask : run_phase
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// Drives a transfer when an item is ready to be sent.
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task reset_driver::drive_tr (reset_transaction tr);
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`uvm_info( get_type_name(),
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$sformatf("Driving reset: delay %0d clocks duration of %0d clocks",
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tr.transmit_delay, tr.duration),
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UVM_LOW)
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// delay
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if (tr.transmit_delay > 0) begin
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repeat(tr.transmit_delay) @(posedge vif.clk);
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end
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// start reset
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vif.reset <= cfg.active_high;
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// duration
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repeat(tr.duration) @(posedge vif.clk);
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// drop reset
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vif.reset <= ~cfg.active_high;
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endtask : drive_tr
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`endif
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22
code/Vezba 13 - prateci materijal/reset_agent/sv/reset_if.sv
Normal file
22
code/Vezba 13 - prateci materijal/reset_agent/sv/reset_if.sv
Normal file
@@ -0,0 +1,22 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_if.sv
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DESCRIPTION reset interface
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****************************************************************************/
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`ifndef RESET_IF_SV
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`define RESET_IF_SV
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/**
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* Interface: reset_if
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*/
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interface reset_if (input clk, output logic reset);
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endinterface : reset_if
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`endif
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@@ -0,0 +1,127 @@
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/****************************************************************************
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
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+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
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FILE reset_monitor.sv
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DESCRIPTION monitors interface for reset; collects coverage
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****************************************************************************/
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`ifndef RESET_MONITOR_SV
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`define RESET_MONITOR_SV
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/**
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* Class: reset_monitor
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*/
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class reset_monitor extends uvm_monitor;
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// reset virtual interface
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virtual reset_if vif;
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// configuration
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reset_config cfg;
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// TLM - from monitor to other components
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uvm_analysis_port #(reset_transaction) item_collected_port;
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// keep track of number of transactions
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int unsigned num_transactions = 0;
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// current transaction
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reset_transaction tr_collected;
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// UVM factory registration
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`uvm_component_utils_begin(reset_monitor)
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`uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)
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`uvm_component_utils_end
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// coverage
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covergroup cg_reset;
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// reset duration
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cp_duration : coverpoint tr_collected.duration {
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bins one_clk = {1};
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bins other = default;
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}
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endgroup : cg_reset;
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// new - constructor
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function new(string name = "reset_monitor", uvm_component parent = null);
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super.new(name, parent);
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item_collected_port = new("item_collected_port", this);
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cg_reset = new();
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endfunction : new
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// UVM build_phase
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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// get configuration object from db
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if(!uvm_config_db#(reset_config)::get(this, "", "reset_config", cfg))
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`uvm_fatal("NOCONFIG",{"Config object must be set for: ",get_full_name(),".cfg"})
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endfunction: build_phase
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// UVM connect_phase
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function void connect_phase(uvm_phase phase);
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super.connect_phase(phase);
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// get interface from db
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if(!uvm_config_db#(virtual reset_if)::get(this, "", "reset_if", vif))
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`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
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endfunction : connect_phase
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// additional class methods
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extern virtual task run_phase(uvm_phase phase);
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extern virtual function void report_phase(uvm_phase phase);
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endclass : reset_monitor
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// UVM run_phase
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task reset_monitor::run_phase(uvm_phase phase);
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forever begin
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tr_collected = reset_transaction::type_id::create("tr_collected");
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// monitor reset
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if(cfg.active_high) begin
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@(posedge vif.reset);
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end
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else begin
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@(negedge vif.reset);
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end
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`uvm_info(get_type_name(), "Reset observed", UVM_MEDIUM)
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tr_collected.duration = 1;
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fork
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// get duration
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forever begin
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@(posedge vif.clk) tr_collected.duration++;
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end
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// monitor reset dropped
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begin
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if(cfg.active_high) begin
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@(negedge vif.reset);
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end
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else begin
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@(posedge vif.reset);
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end
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end
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join_any
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disable fork;
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item_collected_port.write(tr_collected); // TLM
|
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// collect coverage if enabled
|
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if(cfg.has_coverage == 1) begin
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cg_reset.sample();
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end
|
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num_transactions++;
|
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end // forever begin
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endtask : run_phase
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// UVM report_phase
|
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function void reset_monitor::report_phase(uvm_phase phase);
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// final report
|
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`uvm_info(get_type_name(), $sformatf("Report: reset monitor collected %0d transfers", num_transactions), UVM_LOW);
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endfunction : report_phase
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`endif
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@@ -0,0 +1,34 @@
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/****************************************************************************
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||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|
||||
FILE reset_pkg.sv
|
||||
|
||||
DESCRIPTION package containing all parameters and includes
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
`ifndef RESET_PKG_SV
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||||
`define RESET_PKG_SV
|
||||
|
||||
/**
|
||||
* Package: reset_pkg
|
||||
*/
|
||||
package reset_pkg;
|
||||
|
||||
import uvm_pkg::*;
|
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`include "uvm_macros.svh"
|
||||
|
||||
`include "reset_config.sv"
|
||||
`include "reset_transaction.sv"
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||||
`include "reset_driver.sv"
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||||
`include "reset_monitor.sv"
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||||
`include "reset_agent.sv"
|
||||
`include "sequences/reset_seq_lib.sv"
|
||||
|
||||
endpackage : reset_pkg
|
||||
|
||||
`include "reset_if.sv"
|
||||
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||||
`endif
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||||
@@ -0,0 +1,42 @@
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||||
/****************************************************************************
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|
||||
FILE reset_transaction.sv
|
||||
|
||||
DESCRIPTION reset sequence item
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
`ifndef RESET_TRANSACTION_SV
|
||||
`define RESET_TRANSACTION_SV
|
||||
|
||||
/**
|
||||
* Class: reset_transaction
|
||||
*/
|
||||
class reset_transaction extends uvm_sequence_item;
|
||||
|
||||
// delay before asserting reset (#clk cycles)
|
||||
rand int unsigned transmit_delay;
|
||||
// duration of reset (#clk cycles)
|
||||
rand int unsigned duration;
|
||||
|
||||
// constraints
|
||||
constraint c_transmit_delay { transmit_delay <= 10; }
|
||||
constraint c_duration { duration inside {[0:5]}; }
|
||||
|
||||
// UVM factory registration
|
||||
`uvm_object_utils_begin(reset_transaction)
|
||||
`uvm_field_int(transmit_delay, UVM_DEFAULT)
|
||||
`uvm_field_int(duration, UVM_DEFAULT)
|
||||
`uvm_object_utils_end
|
||||
|
||||
// new - constructor
|
||||
function new (string name = "reset_transaction");
|
||||
super.new(name);
|
||||
endfunction : new
|
||||
|
||||
endclass : reset_transaction
|
||||
|
||||
`endif
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||||
@@ -0,0 +1,31 @@
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||||
/****************************************************************************
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|
||||
FILE reset_base_seq.sv
|
||||
|
||||
DESCRIPTION base sequence
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
`ifndef RESET_BASE_SEQ_SV
|
||||
`define RESET_BASE_SEQ_SV
|
||||
|
||||
/**
|
||||
* Class: reset_base_seq
|
||||
*/
|
||||
class reset_base_seq extends uvm_sequence #(reset_transaction, reset_transaction);
|
||||
|
||||
// UVM factory registration
|
||||
`uvm_object_utils(reset_base_seq)
|
||||
|
||||
// new - constructor
|
||||
function new(string name = "reset_base_seq");
|
||||
super.new(name);
|
||||
endfunction : new
|
||||
|
||||
endclass : reset_base_seq
|
||||
|
||||
`endif
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
/****************************************************************************
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|
||||
FILE reset_seq.sv
|
||||
|
||||
DESCRIPTION sequence for assertion reset
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
`ifndef RESET_SEQ_SV
|
||||
`define RESET_SEQ_SV
|
||||
|
||||
/**
|
||||
* Class: reset_seq
|
||||
*/
|
||||
class reset_seq extends reset_base_seq;
|
||||
|
||||
// delay before asserting reset (#clk cycles)
|
||||
rand int unsigned transmit_del;
|
||||
// duration of reset (#clk cycles)
|
||||
rand int unsigned duration_time;
|
||||
|
||||
// UVM factory registration
|
||||
`uvm_object_utils(reset_seq)
|
||||
|
||||
// constraints
|
||||
constraint c_transmit_delay { transmit_del <= 10; }
|
||||
constraint c_duration_time { duration_time inside {[1:5]}; }
|
||||
|
||||
// new - constructor
|
||||
function new(string name = "reset_seq");
|
||||
super.new(name);
|
||||
endfunction : new
|
||||
|
||||
// sequence generation logic in body
|
||||
virtual task body();
|
||||
// send one transaction
|
||||
`uvm_do_with(req, { req.duration == duration_time;
|
||||
req.transmit_delay == transmit_del; } )
|
||||
endtask : body
|
||||
|
||||
endclass : reset_seq
|
||||
|
||||
`endif
|
||||
|
||||
@@ -0,0 +1,18 @@
|
||||
/****************************************************************************
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|F|u|n|c|t|i|o|n|a|l| |V|e|r|i|f|i|c|a|t|i|o|n| |o|f| |H|a|r|d|w|a|r|e|
|
||||
+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+ +-+-+ +-+-+-+-+-+-+-+-+
|
||||
|
||||
FILE reset_seq_lib.sv
|
||||
|
||||
DESCRIPTION sequence includes
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
`ifndef RESET_SEQ_LIB_SV
|
||||
`define RESET_SEQ_LIB_SV
|
||||
|
||||
`include "sequences/reset_base_seq.sv"
|
||||
`include "sequences/reset_seq.sv"
|
||||
|
||||
`endif
|
||||
Reference in New Issue
Block a user